In the matter of semiconductor technology, TSMC is really getting better and better and stronger, and it has almost opened up Intel, which wants to play with everything. According to media reports, as the world’s No. 1 foundry, TSMC has begun mass production of the sixth-generation CoWoS wafer-level chip packaging technology, greatly improving the integration level.
We know that today’s high-end semiconductor chips are becoming more and more complex, and traditional packaging technologies can no longer be satisfied. Intel, TSMC, Samsung, etc. have developed various 2.5D and 3D packaging technologies to integrate and package different IP modules in different ways. in one chip, thereby reducing manufacturing difficulty and cost.
The full name of CoWoS is Chip-on-Wafer-on-Substrate. It is a technology that encapsulates chips and substrates together, and is carried out at the wafer level. Currently, only TSMC grasps it, and the technical details are trade secrets.
It belongs to 2.5D packaging technology and is often used in the integrated packaging of HBM high-bandwidth memory, such as AMD Radeon VII game cards and NVIDIA V100 computing cards.
CoWoS package structure diagram
Radeon VII integrates four HBMs
Of course, TSMC will not disclose the details of the sixth-generation CoWoS, only that it can integrate up to 12 HBM memories in a single package.
The latest HBM2E can already achieve a single capacity of 16GB, and 12 pieces are packaged together, which is a massive 192GB!