“Today, the development of DRAM technology faces many of the same challenges as CPUs, including multiple graphics, proximity effects, and storage node leakage. The development of DRAM requires accurate modeling to predict the impact of the aforementioned problems and make corresponding optimizations to avoid loss of yield. For example, when determining the contact area between the bit line (BL) and the active area (AA), special attention must be paid to the bit line core axis spacing and mask offset. A slight negligence may lead to yield problems.
The development background of semiconductor memory
The world’s earliest fully Electronic memory is the Williams-Kilburn tube (Williams-Kilburn tube), which was born at the University of Manchester in 1947. The principle is to use a cathode ray tube to leave “points” on the surface of the screen “. Since then, computer memory began to use magnetic storage technology and has undergone several generations of evolution. Related systems include drum storage, magnetic core storage, tape drives, and bubble storage. Since the 1970s, mainstream integrated semiconductor memory has been divided into three categories: dynamic random access memory (DRAM), static random access memory (SRAM) and flash memory.
Computer memory is mainly DRAM and SRAM. Compared with the two, DRAM has a higher storage density, while SRAM has the fastest on-chip cache. Both types of semiconductor memory have experienced decades of development. DRAM needs to be refreshed periodically to maintain the stored data. Its development is mainly affected by storage density and cost. SRAM does not need to be refreshed periodically to latch the “0” and “1” signals. The main factors affecting its development are the cell area and read speed.
DRAM technology is derived from the earlier random access memory (RAM). Before the advent of DRAM, RAM was a familiar form of memory. Its characteristic was that it could only save the data being read/written, and erase all the memory once it was turned off and power off. The earliest RAM system consisted of complicated wires and magnets, bulky and power-consuming, basically not practical. IBM’s Robert Dennard (Robert Dennard) changed this situation, he invented the RAM memory cell using a single transistor and storage capacitor. It is based on his outstanding invention that we have gradually developed a single chip that can accommodate one billion or more RAM cells in modern computers.
Challenges faced by semiconductor memory and countermeasures
Today, the development of DRAM technology faces many of the same challenges as CPUs, including multiple graphics, proximity effects, and storage node leakage. The development of DRAM requires accurate modeling to predict the impact of the aforementioned problems and make corresponding optimizations to avoid loss of yield. For example, when determining the contact area between the bit line (BL) and the active area (AA), special attention must be paid to the bit line core axis spacing and mask offset. A slight negligence may lead to yield problems.
It is difficult to find the cause of wafer-level failure and determine the process parameters related to it only by relying on wafer-based experiments. Manufacturing test wafers and measuring the final contact area on the wafers in process change research is time-consuming and costly. Advanced process modeling technology can help us solve the aforementioned problems. By modeling the thickness change of the BL spacer layer and the displacement of the BL mask at the same time, based on the DoE (design of experiment) statistical change study, the minimum contact area can be determined. Based on the results of the aforementioned research, combined with the built-in structure search/DRC function, the minimum contact position and area on the specific chip can be determined. SEMulator3D® is a process modeling platform that can complete the above research. Research on process changes based on this platform can help us find potential problems related to the spacing of the BL mandrel thickness and mask conversion. Figure 1 (a) shows how the SEMulator3D is used to check the BL gap thickness and mask conversion on the BL/AA contact area, while Figure 1 (b) shows the location of the smallest contact area on the chip.
Figure 1. (a) The relationship between the BL/AA contact area, the thickness of the BL interval and the mask offset; (b) the minimum contact area and its location.
DRAM process development should also pay attention to the distance between the storage node and the adjacent active area, because excessive proximity can cause short circuits in the device. Once a short circuit occurs, the root cause behind it is difficult to determine. But if it is not resolved, these problems may lead to serious reliability and yield problems in the later stages of development. If we can determine the minimum gap between capacitor contacts and AA at different z positions through accurate modeling before trial production, we may be able to avoid the aforementioned serious consequences. Figure 2 shows the contact area from BL to AA determined in the process of process modeling, where the highlighted part is the minimum gap problem that needs to be resolved through process or design changes. Through the examples in the figure, it can be seen that the complex interactions between the process steps will ultimately affect the reliability and yield of the DRAM. Therefore, it is meaningful to determine these effects through accurate modeling.
Figure 2. Virtual modeling of the wafer manufacturing process (SEMulator3D). There may be a short circuit between the storage node contacts and AA shown in the figure.
Flash memory that supports multiple erasing and repeated programming appeared in 1984, and it has been used for storage and data transmission in various consumer devices, enterprise systems, and industrial applications. Flash memory can store data for a long time, even if it is turned off and power is off, its manufacturing technology has now shifted from 2D to 3D (ie 3D NAND) to increase storage density.
The etching of a single-layer 3D NAND structure is very complicated, because the high aspect ratio must be etched in a set of alternating materials, while avoiding bending and tilting of the etching holes, and special etching is required to separate adjacent storage The “slit” of the unit. The etching of the complete 3D NAND structure is even more complicated because it also includes the “ladder” etching necessary to form the word line (WL) contacts. Figure 3 shows a complete 3D NAND array modeled with SEMulator3D. It can be seen that the most advanced 3D NAND memory structure is quite complex, and it is only a single-layer structure.
Figure 3. Single-layer 3D NAND memory cell modeled using SEMulator3D.
The complexity of the process has sharply increased in the transition from 2D to 3D flash memory structures, because the 3D structure requires the etching of multiple layers of channels. Most 3D NAND memories today have two layers, which means that the top and bottom layers may be misaligned. Figure 4 shows the problems and challenges faced by multi-layer 3D NAND channel etching.
Figure 4. SEMulator3D output result, which shows the layering dislocation problem and the channel etch offset caused by it.
This is the layer dislocation and the channel etch offset caused by it. This dislocation may be caused by process differences, and is a problem that cannot be avoided in any 3D NAND process development. It can be seen from the example in the figure that the consistency between layers has a very significant impact on the structural quality of the multilayer 3D NAND memory cell. As in the case of DRAM, we can study the DoE statistical change for the layer misalignment of 3D NAND in the SEMulator3D system, and only need to take corrective measures based on the analysis results, without spending time and money on wafer testing.