Simulation to see the parasitic conduction problem in the parallel connection of SiC single transistors

[Introduction]This WeChat article has been conceived for a long time. To pave the way, two basic articles have been published in 2020 and 2021. In 2022, let’s talk about parasitic conduction in SiC single-tube parallel connection again.

This WeChat article has actually been conceived for a long time. To pave the way, two basic articles have been published in 2020 and 2021:

● 2020 “Simulation of Parasitic Conduction of SiC Single Tubes to See the World”

● 2021 “Simulation to see the world of SiC MOSFET single-tube parallel current sharing characteristics”

In 2022, let’s talk about parasitic conduction in SiC single-tube parallel connection again.

Special reminder: Simulation is only a tool, simulation cannot replace experiment, and simulation is for reference only.

Before starting the grand prologue of the simulation, we may wish to review some of the previous small conclusions:

2020 “Simulation to see the parasitic conduction phenomenon of SiC single tube in the world”

● Mechanism clarification: The parasitic turn-on phenomenon comes from the combined effect of Miller capacitance and source inductance.

● Encapsulation Impact: Everything has two sides. The power source inductance in the TO247-3 package is also in the driving loop, which makes the difference in Vgs waveform inside and outside the package easy to cause misjudgment and increase the switching loss, but the advantage is that the switching speed and di/dt are reduced, which is also objectively weakened Risk of source inductance to parasitic turn-on. The Kelvin structure of the TO247-4 package decouples the source inductance of the power loop and the drive loop, and the Vgs inside and outside the package are the same (the inside and outside are the same). Although the switching loss is reduced, the switching speed and di/dt are increased, which is objectively also exacerbates the risk of source inductance to parasitic turn-on. Overall, TO247-4 is a better choice.

2021 “Simulation to see the world of SiC MOSFET single-tube parallel current sharing characteristics”

● In the simulation of the current sharing characteristics of TO247-4pin SiC single transistors in parallel, the source inductance Lex of the main circuit has the most significant impact on the device current sharing, and also forms the source circulating current.

● The device current sharing difference caused by the source inductance Lex can be remedied by the auxiliary source resistance Rgee and the gate-level capacitance Cgs, and its effect is limited. Therefore, at the beginning of the SiC parallel layout, it is necessary to ensure that the source inductance Lex is as consistent as possible.

In order to understand the parasitic conduction problem in the parallel connection of SiC single transistors, we will continue to go through the simulation, layer by layer:

● Relationship between parasitic conduction and source circulating current in SiC single-tube parallel connection

● Since “source circulation cannot be stopped”, what should we do?

01 Select the simulation research object

SiC MOSFET: IMZ120R045M1 (1200V/45mΩ),

TO247-4pin, two parallel

Driver IC:

1EDI40I12AF, single channel, magnetic isolation,

Drive current ±4A(min)

02 Simulation circuit Setup

As shown in Figure 1, based on the idea of ​​double pulses, a main circuit and a driving circuit with two parallel tubes are built, and relevant stray parameters are set, and the ambient temperature is room temperature.

1. External main circuit

DC source 800Vdc, bus capacitance Capacitor (including parasitic parameters), stray inductance Ldc_P and Ldc_N between bus capacitance and half-bridge circuit, double pulse inductance Ls_DPT

2. Parallel main circuit

The whole is a half-bridge structure, and the lower-bridge SiC MOSFET is driven by double pulses to commutate with the upper-bridge SiC MOSFET Body Diode. The lower bridge is two IMZ120R045M1s Q11 and Q12, which are connected in parallel through their respective emitter (source) inductors Lex_Q11 and Lex_Q12, and their respective collector (drain) inductors Lcx_Q11 and Lcx_Q12; the same is true for the parallel structure of Q21 and Q22 of the upper bridge Also a similar connection.

3. Parallel drive circuit

Based on the Kelvin structure of TO247-4pin, the power emitter and the signal emitter can be decoupled from each other. In addition, the 1EDI40I12AF driver chip is equipped with OUTP and OUTN pins, so the driver part of each single tube has its own Rgon , Rgoff and Rgee (auxiliary source resistance) are connected in parallel with the corresponding pins of the secondary side of the driver IC.

4. Drive part settings

Adjust the gate voltage Vgs=+15V and Vgs=0V~-3V by adjusting the secondary side power supply and voltage regulator circuit of the driver IC, and then set the gate resistors Rgon, Rgoff, and the auxiliary source resistor Rgee to 0Ω (1pΩ) by default. , plus the PCB trace inductance Lgon/Lgoff/Lgee between the single-tube gate and the driver IC.

Simulation to see the parasitic conduction problem in the parallel connection of SiC single transistors

Figure 1. Schematic diagram of dual-pulse simulation setup of SiC MOSFETs in parallel (driving one and pushing two)

03 The relationship between parasitic conduction and source circulating current in SiC single-tube parallel connection

Before the simulation, properly transform Figure 1 to Figure 2, and then combine the structure of TO247-4 Kelvin Pin, so that everyone can clearly see the so-called source circulation position. The green Loop TOP1/2 is the loop of the parallel upper tube, and the blue Loop BOT1/2 is the loop of the parallel lower tube. Taking the Loop TOP with parallel upper tubes as an example, Loop TOP1 is mainly composed of main power package external source inductance Lex, package internal source inductance (not shown in the figure) and auxiliary source inductance Lgee, etc. Loop TOP2 is mainly composed of driver The gate resistor Rg, the Inductor Lg, and the auxiliary source resistor Rgee and the inductor Lgee are formed. It is not difficult to imagine that as long as there is a little “trigger” of the source inductance Lex of the main loop or the current di/dt difference, it will be amplified and projected into the corresponding loop, directly or indirectly affecting the gate-level Vgs voltage inside the parallel device.

Figure 2. Loop schematic diagram of parallel upper and lower tubes transformed from Figure 1

The specific process is analyzed through simulation examples:[下管双脉冲,上管关断]

The gate level setting Vgs=+15V/-3V, the parallel source inductance of Q1 and Q2 is set to 8nH first, and then the Lex inductance of Q11 and Q21 is changed to 5nH, as shown in Figure 3, to create a parallel source inductance Lex The difference, see the change of the switching waveform.

Figure 3. Inductor and Resistor Settings for Parallel Simulation

Figure 4. Shutdown Process Simulation Waveforms

As shown in Figure 4: The simulation waveform of the turn-off process, the dotted line is the waveform of the source inductance Lex of the parallel branch is 8nH, the solid line is the waveform of the parallel branch where Lex=5nH of Q11 and Q21.

Figure 5. Simulation waveform of turn-on process

As shown in Figure 5: The simulation waveform of the turn-on process, the dotted line is the waveform of the source inductance Lex of the parallel branch is 8nH, the solid line is the waveform of the parallel branch where Lex=5nH of Q11 and Q21.

From the simulation of the above switching process, it can be seen that the source inductance not only affects the Id and Esw characteristics of its own Q11/Q12, but also significantly affects the Vgs voltage spike (undershoot and overshoot) of the transistor Q21/Q22, especially the overshoot part, as shown in the figure 5, which not only raised the Vgs voltage spike of Q21/Q22 by 2V, but also caused a continuous oscillation of Vgs.

In order to verify the adverse effect of the source circulating current on the above-mentioned overshoot, we added a set of simulations, and changed the driving mode of the upper tube in parallel from one to drive two to a single drive to one, and the lower tube remained unchanged, so as to cut off the upper tube. The loop in which the tubes are connected in parallel, as shown in Figure 6:

Figure 6. The upper tube is changed to a separate one-drive-one parallel drive mode

Figure 7. Turn-on waveform after only the upper tube is changed to a single-drive-one parallel drive mode

In FIG. 7 , the dotted line is the waveform of the source inductance Lex of the parallel branch is 8nH, the solid line is the waveform of the parallel branch where Lex=5nH of Q11 and Q21, and Lex=8nH of Q12 and Q12. The difference in source inductance Lex, in the independent drive mode, hardly raises the overshoot voltage spike. Comparing Figure 5 and Figure 7, when the source loop of the upper tube is cut off, the peaks and oscillations of the overshoot waveform are significantly improved.

For further comparison and explanation, it is added that the parallel connection of a group of upper and lower tubes is changed to the simulation and waveform of independent driving, as shown in Figure 8 and Figure 9:

Figure 8. The upper and lower tubes are all driven in parallel with a single drive and a parallel drive

Figure 9 The turn-on waveform of the parallel drive mode where the upper and lower tubes are both independent and one-drive-one

In FIG. 9 , the dotted line is the waveform of the source inductance Lex of the parallel branch is 8nH, the solid line is the waveform of the parallel branch where Lex=5nH of Q11 and Q21, and Lex=8nH of Q12 and Q12. The waveform conclusion is similar to Figure 7. Since the lower tube also adopts an independent parallel drive mode, the current sharing and loss difference of the lower tube are also very well controlled.

Therefore, based on the comparison and analysis of the above simulation waveforms, it can be seen that when SiC single transistors are connected in parallel, due to the existence of the source loop in the parallel circuit, when the source inductance Lex is different, it will cause the formation of source circulating current and raise the overshoot voltage. spikes, further increasing the risk of Vgs parasitic turn-on. At the same time, the source circulating current will also have an impact on its own Vgs, thereby affecting the current Id sharing and the difference in loss Esw.

04 Since “source circulation cannot be stopped”, what should we do?

It can be seen from the above that in the parallel application of SiC single transistors, whether it is the current sharing or the deterioration of parasitic conduction, the source loop and the circulating current are “caused”, especially in the common parallel mode of one drive and many, almost “There is nowhere to run.” So in practical applications, since “source circulation cannot be stopped”, what should we do to reduce the risk of parasitic conduction?

Strategy 1

Make the Lex inductor as symmetrical as possible

When designing the PCB layout or busbar in parallel, try to achieve the symmetry of the external source inductance of the device as much as possible. For complex multi-parallel cases, finite element tools (such as Q3D) can be used to extract stray inductances to assist in optimal design.

Strategy 2

Add some suppression and remedial measures

Let’s first look at the effects of several common measures through simulation:

○ Use the individual drive mode

Compared with the one-drive-two driving mode, the single drive mode can fundamentally cut off the source loop and completely decouple the source loop from the parasitic conduction (as shown in Figure 8 and Figure 9), but there are also some shortcomings : For example, the cost of multiple driver ICs increases, and the difference in output delay time of different driver ICs leads to asynchronous driving, etc. Especially for high-speed devices such as SiC, special care must be taken.

○ Appropriately increase the gate-level Cgs capacitance

Figure 10. Simulation Setup parameter settings for adding gate-level Cgs capacitance

The simulation Setup parameter settings are shown in Figure 10, and the difference between the parallel Lex is 5nH and 8nH, and the turn-on waveform changes before and after adding gate-level Cgs capacitors are observed. the turn-on waveform.

Figure 11. Comparison of turn-on waveforms before and after adding a 2.2nF capacitor at the gate level

From the above, it can be seen that Cgs reduces the overshoot voltage spike of the upper tube Vgs from 2V to 0V at the expense of reducing the turn-on speed and increasing the Eon loss, and also greatly reduces the Vgs voltage oscillation. The suppression effect on parasitic conduction is still good. (but almost no effect on the Eon parallel difference).

○ Reasonably match the auxiliary source resistance and inductance

Figure 12. Example 1 for setting the auxiliary source resistor Rgee parameter

The simulation Setup parameter settings are shown in Figures 12 and 14. The difference between the parallel Lex is 5nH and 8nH, and the turn-on waveform changes before and after the auxiliary source resistor Rgee is configured are observed. Figure 13: The dotted line is without Rgee, the solid line is the turn-on waveform with Rgee, and the auxiliary source resistance Rgee pushes up the overshoot voltage instead; Figure 15 is the turn-on waveform before and after optimizing the auxiliary source inductance Lgee, the dotted line is Lgee=20nH , the solid line is Lgee=5nH, the inductance reduction can appropriately reduce the overshoot voltage spike.

Figure 13. Comparison of turn-on waveforms before and after adding auxiliary source resistance 1

Figure 14. Example 2 of Optimizing Lgee Parameters of Auxiliary Source Inductance

Figure 15. Comparison of turn-on waveforms before and after optimizing auxiliary source inductance Lgee parameters 2

If the ratio of auxiliary source resistance to gate resistance is appropriately increased, what is the effect? A set of simulation comparisons are added here, as shown in Figures 16 and 17. From the waveform point of view, they are basically similar to the previous two sets of simulation results.

Figure 16. Example 3 of adding auxiliary source resistance Rgee and inductor Lgee parameters

Figure 17. Comparison of turn-on waveforms before and after adding auxiliary source resistance Rgee and inductor Lgee 3

Combining the above simulation waveforms, it can be seen that the auxiliary source resistance Rgee and the inductance Lgee have a general effect on the parasitic conduction suppression at the turn-on time. Even if the Lgee inductance is not well controlled, it will increase the overshoot voltage spike and increase the risk of parallel parasitic conduction. The Eon difference doesn’t help either.

○ Adopt driver IC with Miller clamp

In order to show the influence of Miller clamp, we have fine-tuned the parameters (Rg and Vgs voltage) appropriately, and selected Infineon 1EDI30I12MF (with Miller clamp function), and set the drive voltage Vgs=15V/0V, as follows Figures 18 and 19 show:

Figure 18. Parameter settings for Miller clamp simulation

Figure 19. Circuit Schematic for Miller Clamp Simulation (Top Tube Section)

Figure 20. Turn-On Simulation Waveforms Before and After Miller Clamp is Enabled

(Miller clamp loop inductance Lx_clamp=2nH)

Figure 21. Simulation comparison of the clamping effect of Miller loop inductance Lx_clamp before and after from 2nH to 5nH

Combining the waveforms in Figure 20 and Figure 21, it can be seen that the Miller clamp can suppress the overshoot voltage spike in parallel to a certain extent, but it cannot control the Vgs oscillation. At the same time, it is necessary to control the parasitic inductance in the Miller clamp loop, which is slightly larger. It may also lead to halving or even worsening the inhibitory effect.

○ Add common mode inductance at gate level

The relevant parameter settings and circuit of the common mode inductance added to the gate stage are shown in Figure 22 below: drive voltage Vgs=15V/0V

Figure 22. Example of simulation parameters for adding common mode inductance at gate level

Figure 23. Schematic diagram of simulation circuit with common mode inductance added at gate level

Figure 24. Simulated turn-on waveforms before and after adding gate-level common-mode inductance

As shown by the waveform in Figure 24, before and after the gate-level common-mode inductance (uH level) is added, the dotted line indicates no common-mode inductance, and the solid line indicates the addition of common-mode inductance. It can be clearly seen that the gate-level common-mode inductance can not only be significantly improved The Vgs voltage spike and oscillation of the overshoot can also effectively control the current sharing and reduce the difference of Eon, and the effect is very good.

○ Add coupled inductance at the power source

The simulation-related parameter settings and circuit of the coupled inductor added to the power source are shown in the following figure: driving voltage Vgs=15V/0V

Figure 25. Example of Simulation Parameters for Adding Coupled Inductors to Power Sources

Figure 26. Schematic diagram of power source adding coupled inductor circuit

Figure 27. Simulated Turn-On Waveforms Before and After Adding Coupling Inductor to Power Source

As shown in Figure 27, after the coupled inductance (uH level) is added to the power source, whether it is the voltage spike of the overshoot of Vgs or the current difference in parallel, it has been solved almost perfectly!

05 Summary of parasitic conduction in SiC single-tube parallel connection

Based on the above simulation analysis, the general conclusion is shown in Figure 28 below:

Figure 28. Summary of parasitic turn-on problems in SiC single-tube parallel connection

Source: Infineon, Author: Zhang Hao

The Links:   1DI480A-055 LTM150XH-L04 PM150RSE120