TraditionI2S—Why include the system clock?
In the past, we’ve occasionally mentioned I2S when discussing audio topics. I’ve mentioned I2S in some of my previous articles, and everyone else mentions it when they do audio research. Simply put, it’s a synchronized method of transferring stereo data from one end to the other.
Most people think that I2S has three signals:
1. Data: input or output data
2. Bitclock (BCK): A signal that establishes the boundary between two adjacent bits in a data stream
3. Left/Right Clock (LRCK)/Wordclock (Wordclock): A slow clock running at the sample rate with a 50% duty cycle that establishes the difference between two adjacent channels (left and right) in the data stream border.
I2The hero behind the S is the master clock (MCK), also known as the system clock (SCK), which is often overlooked by digital signal processor (DSP) programmers and other processor enthusiasts. Master clock (MCK/SCK), usually a 64, 128, 256 and 512 times sampling rate (FS) clock. It can be provided directly from an input pin or generated internally in some devices through a phase-locked loop (PLL).
In general, DSPs don’t need an audio master clock because they can process data at a completely different rate and then, driven by BCK and LRCK, get the data into the output buffer (or through the input buffer) at some rate. receiver to receive data).
If you can take your attention away from your processor for a while, you’ll find that the audio master clock is much more important. Most MCK/SCK input audio converters require clock synchronization, while some allow out-of-phase. This means that they need to be supplied by the same high-speed clock, which is then divided. Some of the customers I’ve dealt with will tell me on a whim: “My ADC needs an MCK, but it’s too far from my DAC. So I’m going to put a crystal next to each converter…” There is this The idea is understandable, but please “don’t do this!”
When you buy a crystal, there is no guarantee that it will be exactly 48.000 kHz. Your analog-to-digital converter (ADC) crystal may run at +5% accuracy, while your digital-to-analog converter (DAC) may run at –5% accuracy. Such precision can have disastrous consequences for your designs! Why is this, the following will tell you.
for audioADC the master clock
Such aspicture1 As shown, a high-speed master clock (eg: 24.576 MHz clock) is used to drive the ADC’s oversampling modulator. After that, the data from the oversampling modulator is decomposed into the sampling rate given by LRCK.
When the ADC is operating in master mode (generating BCK and LRCK as outputs), the ADC simply divides the MCK/SCK to generate the LRCK and BCK signals. That’s right! LRCK/BCK and master clock are synchronized – phase may also be synchronized (unless it is a special divider).
picture1 UniversalADC Structure diagram
If it is a slave, and the master clocks are not synchronized, it will produce too much or too little data for the digital decimator to just fit on the output word. Under such conditions, many ADCs will refuse to stream data.
The same goes for DACs.picture2 A high-level DAC block diagram is shown. Here, the interpolator needs to be run through the MCK/SCK, which also drives the delta-sigma modulator. If MCK/SCK is not an integral multiple of the sample rate (64/128/256/512), erroneous data may appear at the output of the delta-sigma modulator.
picture2 UniversalDAC Structure diagram
Where am I/how to generateMCK/SCK Woolen cloth?
In today’s industrial applications, CMOS oscillators are supported by and next to many crystal oscillators. They all have very good accuracy and low jitter. Voltage-controlled oscillators (VCOs) are occasionally used, but they suffer from jitter on their outputs.
Many modern audio converters now integrate a PLL to generate MCK from slow BCK. It works great. However, you should be aware that there is always the potential for jitter when using a PLL, which can degrade audio performance.
Also, I recommend that if you choose between a crystal source driving the ADC or the DAC, you choose to run the ADC from a crystal source. If the input is bad, nothing you do will help! (Like you can’t polish slime bright!)
Therefore, the principles of my advice are:
1. If the converter is an I2S slave, you must provide all three I2S clocks (MCK, BCK, and LRCK) from the same source (or internal PLL if the converter has one).
2. If the converter is an I2S master device, make sure it can provide a reliable jitter-free MCK source. Then, let the converter assign itself. When possible, run the ADC in master mode from a reliable low-jitter MCK source. Doing so ensures minimal jitter and minimal high frequency distortion.
· About Jitter, by Dan Lavry, Lavry Engineering, Copyright © 1997.