Optimization of output voltage waveform of digital power supply UCD92xx

/a>UCD92xx” title=”UCD92xx”>UCD92xx” title=”UCD92xx”>UCD92xx and UCD7xxx non-isolated digital power supplies, the output voltage of the non-isolated digital power supply often appears “step” during the soft start stage, and the waveform is not smooth, especially the output voltage When set to a lower value, such as 1.0V. This “step” phenomenon is related to the design principle of UCD92xx soft start, but it can be optimized and finally solved by certain measures. In this paper, optimization and analysis are carried out from the two directions of UCD92xx loop and minimum duty cycle width, and finally achieved ideal results.

1,Soft start principle and output voltage waveform to be optimized

The soft start of the digital power supply UCD92xx is realized by increasing the reference voltage in a stepwise manner, and the whole process is automatically completed by the software inside the chip. When testing a single board based on UCD9224 and UCD74120, it is found that the output voltage waveform has obvious “step” phenomenon in the soft-start stage, and the waveform is not smooth.

1.1 Introduction to the principle of soft start of digital power supply

Figure 1 shows the power branch and control branch of the digital power supply UCD92xx. The control branch is mainly integrated in the UCD92xx chip, including error generation and analog-to-digital conversion, loop compensation, PWM calculation and generation, etc. Among them, the setting of the reference voltage (VREF) voltage is also included in the control branch.

According to the software algorithm, in the soft-start stage, VREF increases every 100us until the soft-start is completed, that is, the output voltage reaches the final set value. For example, if the output voltage is set to 1.0V and the soft-start time is set to 4ms, the output voltage will increase by 25mv each time during the soft-start phase until it reaches 1.0V.

Optimization of output voltage waveform of digital power supply UCD92xx

picture1: Digital Power Stage and Control Stage Block Diagram

1.2 Output voltage waveform to be optimized

Figure 2 shows the output voltage waveform. It can be observed that the output voltage waveform is not smooth enough in the soft-start stage, and there is an obvious “step” phenomenon.

The waveform was measured on a reference version based on the UCD9224 and UCD74120. The main test conditions are: the test environment is at room temperature, the input voltage is 12V, the output voltage is 1.0V, and the output terminal is loaded with 20A. In addition, the detailed configuration of the digital loop during testing is described in Section 2.4 below.

picture2: Output voltage waveform

1.3 The output voltagestepsPreliminary Analysis of Phenomenon

Figure 3 shows the output voltage waveform observed when the time axis is expanded. Through the measurement, it can be seen that the output voltage increases once every 100us, and the increase range is about 23mV, which is basically consistent with the theoretical calculation value of 25mV.

It can also be observed that each increase in output voltage is done quickly rather than slowly. Analysed from the power stage branch, this is due to the rapid increase in duty cycle. From the analysis of the control-level branch, the reason can be initially attributed to the loop being too fast.

picture3: Step width of output voltage

2 Digital Power Analog Front End and Loop

The digital power control loop includes modules such as analog front end and digital loop compensation, which need to be considered comprehensively when configuring the loop. Among them, the digital loop also includes a nonlinear gain module, which can effectively improve the dynamic response performance of the entire power supply after enabling.

2.1 Digital Power Analog Front End (AFE)

The circuit in the red box in Figure 4 is a part of the analog front end (Analog-Front End, AFE) of the digital power supply, and its gain can be set to four different values ​​such as 1, 2, 4, and 8. Set different gains, the output precision of ADC will also be different. For example, if the gain is set to 4, the output precision will be 2mV; if the gain is set to 1, the output precision will be 8mV.

With the same input error (VEAP-VEAN), different AFE gain values ​​will directly affect the loop performance. The influence trend is that the larger the gain, the wider the loop bandwidth.

picture4: Analog front-end for digital power

2.2 digital power loop

Figure 5 shows the loop block diagram of the digital power supply. where, enis the output of the error amplifier, which is a digital signal; ynIt is the output of the loop, which is also a digital signal, and is input to the PWM module.KNLR The block is a nonlinear gain block, which can be enabled or disabled, and will be analyzed in detail in the next section. a1, a2, b0, b1, b2 are the coefficients for loop compensation, allowing the user to modify to suit different power stage designs. It should be noted that there are two sets of a1~b2 parameters in UCD92xx, which are respectively used in the soft start stage and the normal operation stage.

picture5: Digital Power Loop Block Diagram

2.3 nonlinear gain

in Figure 5KNLRThe module is the nonlinear gain module, and its detailed block diagram is shown in Figure 6. When en does not exceed lim0, the gain is Gin0; when en exceeds Lim0 but does not exceed lim1, the gain is Gain1; and so on. The nonlinear gain module performs different degrees of amplification according to the output of the error amplifier, which can effectively improve the dynamic response performance. If Gain0 is set to 1, even if the nonlinear gain block is enabled, it will not affect the loop specification. If Gain0 is modified from 1 to 0.75 or 1.25, it will affect the loop index. The influence trend is that the larger the gain, the wider the loop bandwidth.

picture6: nonlinear gain block

2.4 Digital Power Loop Configuration

Figures 6 and 7 are software screenshots of configuring the loop using the digital power development tool Fusion Digital Power Designer. This tool can simulate the entire loop and give the closed-loop loop indicators after configuration, including cutoff frequency, phase margin and gain margin, which greatly facilitates the debugging and optimization of the loop.

Figure 6 shows the loop configuration at soft start. The zero-pole information is in the “Linear Compensation” box, where the Gain of the AFE is set to 4×; the nonlinear gain is enabled in this configuration, and the Limit and Gain values ​​are allowed to be modified by the user. Finally, the indicators of the entire loop are 23.87KHz (cutoff frequency), 49.33° (phase margin), and 11.77dB (gain margin).

Figure 7 shows the loop configuration during normal operation. The zero-pole information is in the “Linear Compensation” box, where the Gain of the AFE is 4×; the nonlinear gain is enabled in this configuration, and the Limit and Gain values ​​are allowed to be modified by the user. Finally, the indicators of the entire loop are 33.7KHz (cutoff frequency), 50.57° (phase margin), and 8.77dB (gain margin).

It is by sampling the above configuration that the output voltage has a distinct “step-like” waveform during the soft-start phase. The following will try to slow down the loop to verify that the soft-start phase waveform can be optimized.

2.5 Optimize loop configuration

Figure 9 is a screenshot of the software after the soft-start loop has been optimized.

The optimization of the loop includes: 1) no longer enable the nonlinear gain, and modify Gain0 from 1 to 0.5; this can reduce the low-frequency gain of the loop, and ultimately reduce the loop bandwidth; 2) Modify the Gain of the AFE from 4 to 1. The loop bandwidth can also be reduced. A gain of 1 will make the output accuracy of the AFE worse, and ultimately affect the output voltage, but considering that the soft-start stage has slightly lower accuracy requirements for the output voltage, the above modification is acceptable.

It should be noted that, in order to ensure the performance (accuracy, dynamic performance, etc.) of the output voltage during normal operation, the corresponding loop parameters during normal operation will remain unchanged.

picture9: Optimize soft-start loop parameters

Figure 10 shows the output voltage waveform after optimizing the loop. It can be observed that the “step” phenomenon in the soft-start phase disappears and the waveform is smooth.

Figure 11 is the output voltage waveform after the time axis is expanded. It can be observed that the step time is still 100us, and the step amplitude is 24mV (basically consistent with the theoretical value of 25mV), but each step is no longer sudden. increase, but slowly increase. Therefore, the output voltage waveform becomes smoother.

picture10: Optimized soft-start waveform11: Expand the time to observe the output voltage waveform

However, in the waveform shown in Figure 10, it can be observed that the output voltage has a positive overshoot at the start-up moment and falls back quickly. Strictly speaking, the overshoot will affect the monotonicity of the output voltage waveform, and in some application scenarios, it will not work. The following will optimize for this overshoot.

3 Adjust the minimum drive time to further optimize the output waveform

After optimizing the loop, the output voltage becomes smoother in the soft-start phase, but there will be an obvious overshoot, which needs to be optimized. This overshoot is eliminated by adjusting the minimum duty cycle width below.

3.1 digital power soft startkick-start

Shown in Figure 12 is the output voltage soft-start schematic of the digital power supply. At the beginning, the output voltage has a rapid rise, called “Kick-start”. The magnitude of the kick-start is calculated according to the following formula:

Vstart =Vin×DRIVER_MIN_PULSE × fsw

Among them, DRIVER_MIN_PULSE refers to the width of the minimum duty cycle sent by UCD92xx, which can be set by the user.

picture12: Output voltage soft start

Taking Figure 10 as an example, the amplitude of the output voltage Kick-start is about 185mV. Its DRIVER_MIN_PULSE is set to 50ns, and the theoretical calculation Kickstart amplitude is: 12V×50ns×300KHz=180mV. The actual value is basically the same as the theoretical value.

3.2 Adjust the minimum duty cycle width

Change the DRIVER_MIN_PULSE from the current 50ns to 5ns to verify whether the overshoot of the output voltage is improved. Figure 13 is the output voltage waveform. It can be observed that the overshoot has disappeared, but at the beginning, the output voltage is no longer smooth.

Analysis of the reasons shows that when DRIVER_MIN_PULSE is set to 5ns, although UCD9224 can issue a drive pulse with a width of 5ns, UCD74120 has a requirement on the width of the minimum duty cycle, and the width of 5ns is not enough to turn on the upper buck tube integrated in UCD74120 , resulting in an unsmooth rise of the output voltage.

picture13: The minimum duty cycle width is modified to5ns The output voltage waveform after

Too small DRIVER_MIN_PULSE will make the output voltage unsmooth at the start; too large DRIVER_MIN_PULSE will bring forward overshoot. Therefore, a balance needs to be found.

Gradually increase the value of DRIVER_MIN_PULSE. When it is set to 43ns, an ideal balance point is reached. The waveform of the output voltage is shown in Figure 14. The output no longer has a forward process, and the output voltage waveforms are compared throughout the soft-start phase. smooth.

At this time, the amplitude of the output voltage Kick-start is about 160mV. Its DRIVER_MIN_PULSE is 43ns, and the theoretical calculation Kick-start amplitude is: 12V×43ns×300KHz=154.8mV. The actual value is basically the same as the theoretical value.

picture14: The final optimized output voltage waveform

4 in conclusion

After optimizing the loop parameters corresponding to the soft start by modifying the gain value of the AFE and disabling the nonlinear gain, the “step” phenomenon of the output voltage can be eliminated, and the waveform can rise monotonically and smoothly. The parameters of the loop in normal operation do not need to be changed, which ensures its high bandwidth, so that the accuracy of the output voltage and the dynamic response and other indicators remain unchanged.

By optimizing the width of the minimum duty cycle, the forward process after kick-start can be eliminated, making the output voltage waveform monotonically smooth.

To sum up the above two kinds of optimization measures, the output voltage waveform can be monotonically smooth in the whole soft-start stage.

5 references

1. UCD92xx-Design-Guide, Texas Instruments Inc., 2011

2. UCD9224 datasheet, Texas Instruments Inc., 2010

3. UCD74120 datasheet, Texas Instruments Inc., 2012

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