【Introduction】Since International Rectifier (IR) pioneered the first monolithic high-voltage driver product in 1989, high-voltage integrated circuit (HVIC) technology has begun to utilize a patented monolithic structure, integrating bipolar devices, CMOS and lateral For DMOS devices, products with breakdown voltages higher than 700V and 1400V were designed; these high-voltage driver chips can operate under bias voltages of 600V and 1200V.
After Infineon’s full acquisition of IR in 2016, Infineon has this multi-year market-proven PN junction isolation (JI) technology, which is a mature, reliable and market-proven technology. Proprietary HVIC and latch-up tolerant CMOS technologies create a reliable monolithic construction. Advanced manufacturing processes produce the most cost-effective products for a variety of applications such as motor control, switching power supplies, and more.
Key benefits of Infineon’s PN Junction Isolation (JI) technology:
❖Maximum drive current up to 4A
❖Precision analog circuits (strict timing/propagation delay)
❖Has the largest number of standard gate drive products in the industry
❖Voltage class: 1200V, 600V, 500V, 200V and 100V
❖Drive structure type: three-phase, half-bridge, single-channel, etc.
❖Best price/performance ratio
Introduction of PN Junction Isolation (JI) Technology
A complete half-bridge driver chip includes a high-voltage-resistant high-side driver circuit and a low-side driver circuit, wherein the high-side driver circuit includes a high-voltage level conversion circuit and a high-voltage floating driver circuit. PN junction isolation technology (JI) uses a “well” type high-voltage floating switch formed by a polysilicon ring to isolate a high-voltage circuit that can “float” 600V or 1200V from other low-voltage circuits on the same silicon chip, so as to pass the low-voltage digital signal to the ground. Direct drive power devices IGBTs and MOSFETs that require high voltage floating switches. Widely used in various common circuit topologies, including buck circuits, synchronous boost circuits, half-bridge circuits, full-bridge circuits and three-phase full-bridge circuits, etc.
The following figure is a cross-sectional view of the LDMOS level conversion circuit and the high and low side drive CMOS.
Internal block diagram and working principle of level-shift high-voltage driver chip
The figure below shows the internal design principle and structure of a typical half-bridge driver chip.
This half-bridge driver chip high-side HVIC includes:
❖ Pulse generator: generate pulse signals on the rising and falling edges of the input signal HIN;
❖Level shift circuit: convert the signal with COM as reference to the signal with VS as reference;
❖SR latch: latch the pulse signal transmitted from the level shift circuit;
❖Buffer: Amplifies the input signal
❖Delay circuit: Compensate the transmission delay of high-side signal;
❖Bootstrap diode: Charge the bootstrap capacitor when S2 is turned on. Through the level conversion circuit, the Hin signal relative to the ground (COM) is converted into a synchronous Ho signal relative to the floating ground (VS), thereby controlling the switch of the high side S1.
VS negative pressure and latch-up
In a half-bridge circuit, inductive load, parasitic inductance, and reverse freewheeling of the lower tube may generate negative pressure on the VS pin. Based on the construction of the HVIC, VS negative pressure may cause the HVIC to fail. Therefore, how to suppress VS negative pressure will be an important issue in HVIC applications.
L1 and L2 are the package inductance of the power devices on the upper and lower tubes and the parasitic inductance of the circuit traces respectively. When the upper tube is turned on, the current flows through the load inductance through the upper tube; when the upper tube is turned off for commutation, the freewheeling current passes through the S2 body diode, and a voltage is generated on the parasitic inductance of L1L2, resulting in a negative voltage lower than the ground voltage at the VS terminal. The magnitude of the negative voltage is proportional to the magnitude of the parasitic inductance and the current turn-off speed di/dt of the switching device; di/dt is determined by the gate drive resistor Rg and the input capacitance Ciss of the switching device.
In addition to making Vbs exceed the absolute maximum rating of the chip, the VS negative pressure will cause the chip to be damaged by overvoltage; more often it will cause a latch-up effect, resulting in unpredictable results.
As shown in the figure above, there is an equivalent diode D1 (VB-COM) from the epitaxial layer of the driver chip to the substrate, and an equivalent NPN transistor Q1 (VCC-COM-VB) in the epitaxial layer-substrate-epitaxial layer. When VS generates negative pressure, D1/Q1 may be turned on, which will cause HO to jump (when there is no input signal, HO may jump from low level to high level), resulting in a short circuit of the half-bridge power tube and the system failure. Or, a latch-up effect occurs in the internal CMOS structure of the driver chip, thereby causing the driver chip to fail.
The above two pictures are a measured double-pulse waveform from the customer. The input signal of the driver chip is low level, but the output jumps to high level. When the upper tube is turned off, the transient voltage of the VS pin reaches -130V. This negative pressure causes HO to jump from low to high.
JI technology driver chip peripheral circuit design guide
In order to reduce -VS(VS=-(Lp*di/dt+Vf)), it is necessary to do in circuit design:
1. Minimize the parasitic inductance, reduce the wiring of the drive loop, and avoid staggered wiring.
2. The two power tubes of the half-bridge circuit should be installed as close as possible, and the connection between them should be as thick and short as possible.
3. The driver chip should be as close to the power tube as possible
4. The decoupling capacitor on the bus power supply should be as close to the power tube and current detection resistor as possible
5. Use a resistor with low parasitic inductance as the current sense resistor, and try to be as close as possible to the power tube below
6. Use ceramic capacitors with low parasitic inductance between VB and VS
7. Ceramic capacitors with low parasitic inductance should also be used between VCC and COM. The recommended capacitance between VCC and COM is more than ten times that of VB and VS.
8. The decoupling capacitor should be as close as possible to the pin of the driver chip
If the above matters are paid attention to, and the negative pressure of the VS pin is still very large, you can consider reducing the switching speed of the power tube in order to reduce the current change rate di/dt during switching, for example:
1. Additional buffer circuit
2. Increase the drive resistance (note: this method will increase the switching loss of the power tube)
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Stepper Motor Evaluation Board for 200V Half-Bridge/High Side and Low Side Level Shift Gate Drivers IRS2005S/IRS2007S/IRS2008S
Level-Shifting Half-Bridge Gate Driver Drive 1200V, 50 A EconoPIM™3 Module Evaluation Board with Desaturation Detection
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In practical applications, due to various limitations, it may be difficult to meet the above design guidelines, resulting in high Vs negative pressure. At this time, you can also choose SOI driver chips with higher negative pressure capability. Please pay attention to our follow-up driver series Introduction to the article.
Original: Wang Gang Li Qingxia, Infineon Industrial semiconductor