The use of edge computing is growing across applications such as the Industrial Internet of Things (IIoT), robotics, medical devices, wearables, artificial intelligence, automotive, and portable designs. Along with this growth is the need for high-speed, low-latency, non-volatile, low-power, low-cost memory for uses such as program storage and data backup. While there are many options available, including static random access memory (SRAM), dynamic RAM (DRAM), flash, and electrically erasable programmable read-only memory (EEPROM), each of these widely used technologies require tradeoffs in one or more areas to that make them less than ideal for edge computing.
Instead, designers can look to magnetoresistive random access memories (MRAMs). MRAM devices, as the name implies, store data in magnetic storage elements and offer true random access, allowing both reads and writes to occur randomly in memory. Their structure and operation are such that they feature low latency, low leakage, high write cycle count, and high retention, all of which are highly desirable for edge computing.
This article briefly compares the performance capabilities of common memory technologies including EEPROM, SRAM, and flash with MRAM. It will then review the benefits of using MRAM in several edge computing applications, and then introduce specific MRAM devices from Renesas Electronics, some MRAM usage tips, and an evaluation platform to help designers get started on their design.
Memory technologies comparison
Designers of edge computing applications have several memory technologies to choose from, each of which offers varying performance capabilities and tradeoffs (Figure 1). DRAM most often provides the working memory for various types of processors during software execution. It is inexpensive, relatively slow (compared with SRAM), consumes significant amounts of power, and retains data only as long as there is power supplied. In addition, DRAM memory cells are subject to corruption by radiation.
SRAM is faster and is more expensive than DRAM. It is often used as the cache memory for processors, while DRAM provides the main memory. It is the most power hungry of the memories being described here, and like DRAM, it is a volatile memory. SRAM cells are subject to corruption by radiation, and both DRAM and SRAM provide high endurance.
EEPROM is a non-volatile memory that uses an externally applied voltage to erase the data. EEPROMs are slow, have a limited endurance—typically up to one million cycles—and are relatively power hungry. EEPROM is currently the least used of the memory technologies being described here.
Flash is a variation of EEPROM, with substantially more storage capacity and with faster read/write speeds, but it’s still relatively slow. Flash is inexpensive, and data survives power-off conditions for up to 10 years. However, flash is more complex to use relative to other memory types. Data must be read in blocks and cannot be read byte by byte. Also, before being rewritten, cells must be erased. Erasure has to be performed block by block, not by individual bytes.
MRAM, for its part, is a true random-access memory; allowing both reads and writes to occur randomly in memory. MRAM also features zero leakage when in standby, and combines the ability to endure 1016 write cycles with a data retention capability of greater than 20 years at 85°C. It is currently offered in density ranging from 4 megabits (Mbits) to 16 Mbits.
MRAM technology is analogous to flash technology with SRAM compatible read/write timings (MRAM is sometimes referred to as persistent SRAM (P-SRAM)). Due to its characteristics, MRAM is particularly suited to applications that must store and retrieve data with minimal latency. It combines this low latency with low power, infinite endurance, scalability and non-volatility. MRAM’s inherent immunity to alpha particles also makes it suitable for devices that are regularly exposed to radiation.
Figure 1: MRAM is non-volatile like flash and EEPROM and has SRAM compatible read/write timings. (Image source: Renesas Electronics)
How MRAM works
As the name implies, data in MRAM is stored by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. This structure is called a magnetic tunnel junction (MTJ). One of the two plates is a permanent magnet set to a specific polarity during manufacture; the other plate’s magnetization can be changed to store data. Renesas Electronics most recently added MRAM devices which use a proprietary spin transfer torque MRAM (STT-MRAM) that is based on a perpendicular magnetic tunnel junction (p-MTJ). The p-MTJ includes a fixed and unchangeable magnetic layer, a dielectric barrier layer, and a changeable ferromagnetic storage layer (Figure 2).
Figure 2: The basic cell of STT-MRAM consists of one MTJ and one accessing transistor. (Image source: Avalanche Technology)
During a programming operation, the magnetic orientation of the storage layer is electrically switched from a parallel state (low resistance state “0”) to an antiparallel state (high resistance state “1”), or vice versa, depending on the current direction through the p-MTJ element. These two distinct resistance states are used for data storage and sensing.
MRAM use cases
Data logging, memories in IoT nodes, machine learning/artificial intelligence in edge computing devices, and RFID tags in hospitals are examples of MRAM use cases.
Data loggers require multiple megabits of non-volatile memory to accommodate long term accumulation of data. They are typically battery powered, but can also rely on energy harvesting for power, and therefore require low-power memory. In the event of power loss, the logged data must be retained indefinitely. MRAM meets the performance demands of data loggers.
MRAM persistence, combined with an extremely low energy mode, is enabling a unified memory solution for code and data in IoT nodes operating from energy harvesters or battery sources in extremely small form factors (Figure 3). Startup time is often an important consideration in IoT nodes. Implementing a code-in-place structure using MRAM can reduce the time required to boot up, as well as overall bill of materials cost since there is less need for DRAM or SRAM.
Figure 3: MRAM’s speed, endurance and data retention capabilities help it meet the memory requirements of IoT nodes. (Image source: Avalanche Technology)
The persistence offered by MRAM is also enabling a new generation of IoT nodes capable of machine learning where the inference algorithms do not have to be reloaded every time after device wakeup. The local processing includes analyzing sensor data, making decisions, and in some cases, even reconfiguring the node. This localized intelligence demands persistent and low-power memory. These devices can implement local coarse inference in real time and can use the cloud for enhanced analysis.
The speed of MRAM is beneficial for implementing machine learning in edge devices such as enterprise resource planning (ERP) systems, manufacturing execution systems (MES), and supervisory control and data acquisition (SCADA) systems. In these systems data is analyzed and intermediate patterns identified and shared with adjacent domains. The edge architecture requires speed of processing and persistent memory.
Designers can also apply MRAM in healthcare devices where radio frequency identification (RFID) can be beneficial. Its low power consumption, combined with its immunity to radiation, make it suitable for hospital environments. RFID tags in hospitals are used for a variety of reasons including inventory management, patient care and safety, medical equipment identification, and identification and monitoring of consumables.
High-performance serial MRAM memory
Designers of edge computing systems including industrial controls and automation, medical devices, wearables, network systems, storage/RAID, automotive, and robotics can use Renesas’ M30082040054X0IWAY (Figure 4). It is available in densities ranging from 4 Mbits to 16 Mbits. Renesas’s MRAM technology is analogous to flash technology with SRAM-compatible read/write timings. Data is always non-volatile with 1016 write cycles endurance and greater than 20 year retention at 85°C.
The M30082040054X0IWAY has a Serial Peripheral Interface (SPI), eliminating the need for software device drivers. SPI is a synchronous serial interface which uses separate lines for data and clock to help keep the host and slave in perfect synchronization. The clock tells the receiver exactly when to sample the bits on the data line. This can be either the rising (low to high) or falling (high to low) or both edges of the clock signal.
Figure 4: The M30082040054X0IWAY offers both hardware and software-based data protection schemes. Hardware protection is through the WP# pin. Software protection is controlled by configuration bits in the Status register. Both schemes inhibit writing to the registers and memory array. (Image source: Renesas)
The M30082040054X0IWAY supports eXecute-In-Place (XIP) which allows completing a series of read and write instructions without having to individually load the read or write command for each instruction. Thus, XIP mode saves command overhead and reduces random read and write access time.
The M30082040054X0IWAY offers both hardware and software-based data protection schemes. Hardware protection is through the WP# pin. Software protection is controlled by configuration bits in the Status register. Both schemes inhibit writing to the registers and memory array. It has a 256-byte Augmented Storage Array which is independent from the main memory array. It is user programmable and can be write protected against inadvertent writes.
To further cater to low-power applications, the M30082040054X0IWAY has two lower power states: Deep Power Down and Hibernate. Data is not lost while the device is in either of these two low-power states. Moreover, the device maintains all its configurations.
The device is available in small footprint 8-pad DFN (WSON) and 8-pin SOIC packages. These packages are compatible with similar low-power volatile and non-volatile products. It is offered with industrial (-40°C to 85°C) and industrial plus (-40°C to 105°C) operating temperature ranges.
MRAM can significantly reduce overall energy consumption compared with other memory technologies. But the amount of energy savings can vary depending on the usage patterns of the specific application design. Like other non-volatile memories, the write current is much higher than the read or standby current. As a result, write times need to be minimized in power-critical applications, especially in designs which require frequent writes to memory. MRAM’s shorter write times can mitigate this consideration and reduce energy consumption compared with other non-volatile memory choices, such as EEPROM or flash.
Additional energy savings are possible with MRAM using a power gating system architecture and placing the memory into standby as often as possible. MRAM’s faster power up to write time makes it possible to put MRAM into standby more frequently than other non-volatile memories. MRAM’s zero leakage when in standby is also a help here. Note that a larger decoupling capacitor is often needed to support power up energy needs when power gating is employed.
MRAM eval board
To help designers get started with the M30082040054X0IWAY, Renesas provides the M3016-EVK evaluation kit. This contains the 16-Mbit MRAM and enables users to develop interactive hardware solutions using the popular Arduino board (Figure 5). The plug-n-play kit features an Arduino host board and terminal emulator software that communicates with the PC computer USB interface. The evaluation board mounts on top of the Arduino UNO host board via the UNO R3 headers. Test programs provided allow users to quickly evaluate the functionality of the MRAM device.
Figure 5: The M3016-EVK evaluation kit mounts on top of an Arduino UNO host board to support fast evaluation of MRAM performance. (Image source: Renesas)
Designing edge computing devices using conventional memory technologies such as DRAM, SRAM, flash, and EEPROM requires a variety of tradeoffs that can limit performance. For edge computing, designers can look to recently introduced MRAMs that offer true random access, allowing both reads and writes to occur randomly in memory.
As shown, MRAM supports the memory needs of edge computing designers including: a device that must store and retrieve data without incurring large latencies; low power consumption due to zero leakage when in standby; and the ability to endure 1016 write cycles with a data retention capability of greater than 20 years at 85°C.
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