Circuit timing is a critical function required by a wide range of Electronic devices including microcontrollers, USB, Ethernet, Wi-Fi, and Bluetooth interfaces, as well as computing devices and peripherals, medical devices, test and measurement equipment, industrial control and automation, the Internet of Things (IoT), wearables, and consumer electronics. Designing crystal-controlled oscillators to provide system timing appears at first to be a simple exercise, but designers must consider numerous parameters and design requirements when matching a quartz crystal to an oscillator IC.
The many considerations include crystal motional impedance, resonant mode, drive level, and oscillator negative resistance. For the circuit layout, the designer needs to consider the pc board’s parasitic capacitance, inclusion of a guard band around the crystal, and the on-chip integrated capacitance. The final design needs to be compact and reliable with a minimum number of components, have low root mean square (rms) jitter, and be able to operate over a wide input voltage range with minimal power consumption.
One solution is to use simple packaged crystal oscillators (SPXOs). Optimized for low power consumption and low rms jitter, plus operation at any voltage between 1.60 and 3.60 volts, these continuous-voltage oscillators enable designers to implement solutions that require minimal design effort to integrate into systems.
This article will briefly discuss some of the important performance requirements and design challenges that must be satisfied to successfully design timing circuits using discrete quartz crystals and timing ICs. It then introduces SPXO solutions from Abracon and shows how designers can use them to effectively and efficiently meet the timing needs of electronic systems.
Crystal oscillator operation and design challenges
Power consumption is an important consideration in small, battery-powered wireless devices. Many such devices are based on very low power system-on-chip (SoC) radios and processors that can support multi-year battery lives. Also, minimizing the size of the battery is important to control device cost since the battery can be the most expensive component in the system. That said, standby current is often the most important battery life consideration in small wireless systems, and the clock oscillator often dominates the standby current. Therefore, minimizing oscillator current draw is critical.
Unfortunately, designing low-power oscillators can be challenging. One way to save energy is to minimize the standby current by entering a “disabled” state and starting up the oscillator as needed. However, crystal oscillators are not simple to start up quickly and reliably. Designers need to take care to guarantee that the oscillator draws low current during standby and has reliable start-up characteristics across all operating and environmental conditions.
The Pierce oscillator configuration is commonly used in low-power wireless SoCs (Figure 1). A Pierce oscillator is built around a crystal (X) and load capacitors (C1 and C2), wrapped with an inverting amplifier using an internal feedback resistor. Under the right conditions, when the output of the amplifier is fed back into the input, it results in a negative resistance and oscillation occurs.
Figure 1: Basic Pierce oscillator configuration built around a crystal (X) and load capacitors C1 and C2. (Image source: Abracon)
Crystals are complex structures; this discussion only provides a top-level and simplified look at their operation in oscillators.
The closed-loop gain margin, Gm, can be used as a figure of merit (FOM) to characterize the reliability of an oscillator relative to various losses. It’s also called the oscillation allowance (OA). An OA under 5 can result in low production yields and temperature-related start-up problems. Designs with an OA of 20 or more are robust, provide reliable operation over the designed operating temperature range, and are insensitive to production lot variations in terms of crystal and SoC performance characteristics.
To measure the OA of an oscillator, a variable resistor, Ra is added to the circuit (Figure 2). The value of Ra is increased until the oscillator cannot start. That is the value used to determine OA as follows:
Rn is the negative resistance
Re is the equivalent series resistance (ESR)
Where the load capacitance, CL, is calculated using:
Where Cs is the circuit vagrant capacitance, usually 3.0 to 5.0 picofarads (pF).
Figure 2: Pierce oscillator showing the expanded crystal model (in the box in the center) and the adjustable resistor (Ra) for measuring the oscillation allowance. (Image source: Abracon)
OA is dependent on the ESR (Re), and the ESR is dependent on the quartz crystal parameter Rm and the load capacitance, CL. The impact of Rm and CL on OA increases for low-power oscillators, such as those used in low-power wireless devices. Measuring OA takes time and can seem to extend the development process. As a result, it can be overlooked, causing performance problems when the system or device enters production.
In addition, setting a high OA to ensure reliable oscillator operation can result in other problems. For example, a high OA will result in high oscillator circuit performance, but power losses due to the crystal can be overlooked. These losses can be a significant factor. Looking back to Figure 2, the crystal motional resistance, Rm, causes power dissipation as the current cycles through the resistance. The current and losses increase when CL is larger. Designers need to achieve a balance between power losses in the crystal and a reasonable value for OA.
When designing quartz crystal oscillators, jitter is important to understand and minimize. There are two types of jitter, both of which are typically measured as rms values:
- Cycle-to-cycle jitter: Also called phase jitter, is the maximum time difference between several measured periods of oscillation, usually measured over a minimum of 10 periods.
- Period jitter: This is the maximum change of a clock edge and is measured at each period, but not multiple periods.
Major sources of jitter in quartz crystal oscillators include power supply noise, integer harmonics of the signal frequency, improper load and termination conditions, amplifier noise, and certain circuit configurations. Depending on the source, there are several methods that can be employed to minimize jitter:
- Use of bypass capacitors, chip beads, or resistor-capacitor (RC) filters to control power supply noise.
- In critical applications that demand very low jitter, it is important to establish a method to control the harmonics (beyond the scope of this article).
- Reduce reflected power back into the output by optimizing the load and termination conditions.
- Avoid using designs that include phase-locked loops, multipliers, or programmable features since they tend to increase jitter.
Continuous-voltage crystal oscillators
Designers of systems with a varying system bias voltage between 1.60 and 3.60 volts can benefit from using the ASADV, ASDDV, and ASEDV SPXOs from Abracon (Figure 3). These SPXO families cover different frequency ranges; 1.25 megahertz (MHz) to 100 MHz for the ASADV devices, and 1 MHz to 160 MHz for the ASDDV and ASEDV devices. They are RoHS/RoHS II compliant and come in hermetically sealed ceramic surface-mount device (SMD) packages. Their frequency stability is ±25 parts per million (ppm) across their operating temperature range of -40°C to +85°C.
Figure 3: The ASADV (shown), ASDDV, and ASEDV SPXOs are packaged in hermetically sealed ceramic packages and can operate from -40°C to +85 °C. (Image source: Abracon)
The ASADV measures 2.0 x 1.6 x 0.8 millimeters (mm), the ASDDV measures 2.5 x 2.0 x 0.95 mm, and the ASEDV measures 3.2 x 2.5 x 1.2 mm. These three series are available with a variety of common operating temperature ranges, stability options, and a CMOS/HCMOS/LVCMOS compatible output format.
Importantly, the ASADV, ASDVD, and ASEDV families are optimized for low-current operation (Figure 4). The output enable/disable function reduces current to only 10 microamperes (μA) when disabled. They have a maximum start-up time of 10 milliseconds (ms).
Figure 4: Shown is the current consumption of the ASEDV versus supply voltage which is typical of the performance of this family of SPXOs (measured at 25°C ±3°C). (Image source: Abracon)
All three families of SPXOs have particularly low current consumption. For the ASADV, the maximum current (measured into a 15 pF load at 25°C) ranges from 1.0 milliamperes (mA) at 1.25 MHz and a supply voltage of 1.8 volts, to 14.5 mA at 81 MHz and a supply voltage of 3.3 volts. For the ASDDV and ASEDV, the maximum current ranges from 1.0 mA at 1 MHz and a supply voltage of 1.8 volts, to 19 mA at 157 MHz and a supply voltage of 3.3 volts.
The devices can drive multiple loads and have good electromagnetic interference (EMI) performance and low jitter. They are specified for rms phase jitter of <1.0 picosecond (ps) and a period jitter of 7.0 ps, maximum.
The SPXOs also provide good frequency stability over their entire operating temperature range (Figure 5). In many applications, these oscillators can be used as drop-in solutions, needing little design work. They also eliminate the need for bias-specific oscillator selection and remove bias-dependent frequency variations.
Figure 5: These SPXOs have good frequency stability over the entire operating temperature range. This graph for the ASEDV family is typical. (Image source: Abracon)
Finally, when shock and vibration are not critical considerations, the ASADV, ASDVD, and ASEDV continuous-voltage surface mount crystal oscillators can be used to provide lower-cost alternatives to microelectromechanical systems (MEMS) oscillators.
Designers need precise and reliable oscillators to provide stable timing across a wide range of applications and operating temperatures. Discrete crystal-controlled oscillators can meet the required performance characteristics, but designing effectively with crystals can be technically difficult, time-consuming, unnecessarily costly, and sub-optimal with respect to form factor.
As shown, designers can instead use integrated, low-power SPXOs that form drop-in timing solutions with good frequency stability over a wide operating temperature range. Using SPXOs, designers can reduce component count, shrink solution size, reduce assembly costs, and improve reliability.
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