Editor’s Note: Analog-to-digital converters (ADCs) connect the analog to the digital world, and so are a fundamental component of any electronic system that connects to the real world. They are also a key determining factor of a system’s performance. This series explores the fundamentals of ADCs, their various types, and their application. Part 1 of this series on analog basics discussed SAR ADCs. Part 2 discusses delta-sigma converters. Part 3 looks at pipeline ADCs. Part 4 shows how delta-sigma ADCs can generate ultra-low-noise results. Here, Part 5 explores difficult input driving issues for SAR ADCs.
Many data acquisition, industrial control, and instrumentation applications require an ultra-high-speed analog-to-digital converter (ADC) when a successive-approximation register (SAR) converter is perfectly suitable. However, it’s essential to ensure the external circuitry around the SAR converter is also up to the task to ensure a successful conversion outcome. The crucial terminals that require special care for the SAR converter are its analog signal inputs—if left unattended, these input pins can produce stability issues and capacitive charge “kickbacks” that can lead to inaccurate conversions and elongated signal acquisition time.
The solution to precise input signal control for SAR converter applications lies in the driving of operational amplifiers (op-amps). These devices, supported by the proper output resistor and capacitor values, are the foundation of a high-precision, robust solution for high-resolution, 16-bit and 20-bit SAR converter systems.
This article briefly discusses the issues associated with achieving stable and accurate SAR ADC conversions. It then introduces an appropriate op amp for driving a SAR ADC and shows how to implement the necessary input driver circuits. Solutions from Analog Devices will be used by way of example.
SAR ADC input circuitry
The SAR ADC driver circuits have op-amps (A1 and A2) that separate the ADC from their signal sources (Figure 1). In this circuit, Rext keeps the amplifier stable by “isolating” the amplifier’s output stage from the ADC capacitive load (CIN+ and CIN-) and Cext. Cext and CREF provide a nearly perfect input source to the ADC that absorbs the switching charge injection from the IN+, IN-, and REF input terminals. The input terminals (IN+, IN-) track the voltage of the input signal (VSIG+, VSIG-) during the converter’s acquisition time, providing charge to the ADC’s input sampling capacitors, CIN+ and CIN-.
Figure 1: In this circuit, Rext “isolates” Cext from the op amp output stage. Cext and CREF provide charge reservoirs for the differential SAR ADC during the sampling period. (Image source: Digi-Key Electronics)
Looking at the ADC’s interior using Analog Device’s AD7915 (16-bit) and AD4021 (20-bit) SAR ADCs as examples, it can be seen to use a charge redistribution digital-to-analog converter (DAC). The capacitive DAC has two identical arrays of binary-weighted capacitors. These arrays connect to the non-inverting and inverting comparator inputs (Figure 2).
Figure 2: A simplified AD7915 and AD4021-based schematic of a SAR ADC, where N is equal to the converter’s number of bits. (Image source: Modified by Digi-Key Electronics from original material from Analog Devices)
During the acquisition phase, the inputs (IN+ and IN-) switch to the capacitive array. Additionally, SW+ and SW− close, tying the least significant bit (LSB) capacitors to ground (GND). In this state, the capacitor arrays become the sampling capacitors, acquiring the IN+ and IN− analog signals. Upon completion of the acquisition phase, the CNV input to the control logic (right side) goes high to initiate the conversion phase.
The conversion phase begins with the opening of SW+ and SW- and switching the two capacitor arrays to GND. In this configuration, the captured IN+ and IN- differential voltage causes the comparator to become unbalanced. The charge redistribution DAC methodically switches each element of the capacitor array from most significant bit (MSB) to LSB, between GND and REF. The comparator input varies by binary-weighted voltage steps (VREF/2N-1, VREF/2N-2 … VREF/4, VREF/2). The control logic toggles the switches from the MSB to LSB, bringing the comparator back to a balanced condition. Upon completion of this process, the ADC returns to the acquisition phase, and the control logic generates the ADC output code.
Input charge injection, circuit stability, and driving the AD7915 ADC
A critical part of the conversion process is to acquire an accurate input signal voltage. The ADC data conversion process runs smoothly when the driving amplifier accurately charges the input capacitors, CIN+ and CIN-, while maintaining stability to the end of the ADC acquisition time. The problem for designers is that the ADC’s input terminal introduces a capacitance (CIN+, CIN-) as well as switching noise or “kickback” charge injection for the driving amplifier to manage.
An amplifier circuit Bode plot quickly estimates the circuit’s stability. The Bode plot tool approximates the magnitude of an amplifier’s open-loop and system closed-loop gain transfer functions (Figure 3).
Figure 3: The open and closed-loop transfer function of the amplifier in Figure 1, without Rext and Cext as amplifier loads and the following SAR ADC. (Image source: Digi-Key Electronics)
The y-axis quantifies the amplifier open-loop gain (AOL) and the closed-loop gain (ACL) of the amplifier circuit, where the amplifier’s AOL curve starts at 130 decibels (dB) and the closed-loop gain, ACL, equals 0 dB. The units along the x-axis logarithmically quantify the open and closed-loop gain frequency from 100 Hertz (Hz) to 1 gigahertz (GHz).
In Figure 3, the amplifier’s DC open-loop gain at approximately 220 Hz (fO) progresses downward from 130 dB at a rate of -20 dB/decade. As the frequency increases, this attenuation rate continues past 0 dB at approximately 180 megahertz (MHz). Since this curve represents a single-pole system, the crossover frequency, fU, is equal to the unity-gain-stable amplifier’s gain bandwidth product (GBWP). This plot represents a stable system because the AOL and ACL closure rate is 20 dB/decade.
The addition of Rext and Cext and the SAR ADC modifies the amplifier circuit by creating a system zero and pole (Figure 4). The system comprises a 16-bit, 1 megasample per second (MSPS) AD7915 differential PulSAR ADC and a 180 MHz, rail-to-rail input/output ADA4807-1 amplifier, both from Analog Devices. The combination of the amplifier and ADC requires Rext due to the 30 picofarad (pF) (typ) ADC input capacitance load. The circuit also requires Cext to act as a charge bucket to provide enough charge at the ADC input to accurately match the input voltage.
Figure 4: Shown is the Bode plot response of two ADA4807 op-amps driving the AD7915 SAR ADC with two separate Rext/Cext pairs. The fP1 and fZ1 corner frequencies modify the open loop gain of the amplifier, creating a stable system response. The fP2 and fZ2 corner frequencies modify the amplifier’s open loop gain, creating a marginally stable response. (Image source: Digi-Key Electronics)
The circuit in Figure 4 can potentially oscillate due to the ADC capacitive load and the ADC’s switching charge injection when the initial acquisition occurs. The additional pole and zero created by the Rext/Cext amplifier output components ensure a stable system, so the open and closed-loop gain curve intersection is greater than 20 dB/decade, rendering a phase margin less than 45°. This configuration, with fP2 and fZ2, creates an unstable circuit.
To prevent instability, when evaluating the amplifier’s open-loop gain curve with Rext and Cext in the circuit, designers need to include the effect of the amplifier’s open-loop output resistance, RO. The combination of RO equaling 50 ohms (W), Rext, and Cext modifies the open-loop response curve by introducing one pole (fP, Equation 1) and one zero (fZ, Equation 2). The values RO, Rext, and Cext determine the corner frequency of fP. The values of Rext and Cext determine the zero-corner frequency, fZ.
The fP and fZ calculations are:
fP1 = 842 kHz
fZ1 = 2.95 MHz
with: RO = 50 W
Rext = 20 W
Cext = 2.7 nanofarads (nF)
fP2 = 22.7 MHz
fZ2 = 79.5 MHz
with: RO = 50 W
Rext = 20 W
Cext = 0.1 nF
The above values for fP1 and fZ1 provide a stable system for the AD7915 and ADA4807-1.
Driving the Easy Drive AD4021 SAR ADC
An alternative to the AD7915 is the AD4021 20-bit 1 MSPS Easy Drive SAR converter. The AD4021 device family greatly reduces input kickback and input current to 0.5 microamperes (μA)/MSPS. The Easy Drive features reduced power consumption and signal chain complexity.
The AD4021’s analog input has circuitry that reduces the typical switched capacitor SAR input nonlinear charge kickback. The kickback reduction, and a longer acquisition phase, allow the use of lower bandwidth and lower power driver amplifiers (Figure 5).
circuitry and acquisition timing of the Analog Devices AD4021″ alt=”Analog Basics—Part 5: Tackling Difficult Input Driving Issues for the SAR ADC”>Figure 5: The input circuitry and acquisition timing of the AD4021 reduce the kickback switching current and relax the driver amplifier’s stringent requirements. (Image source: Analog Devices)
The combination of kickback reduction and longer acquisition time also allows a larger Rext resistor value in the input resistor-capacitor (RC) filter and a corresponding smaller Cext capacitor. This combination of a smaller Cext amplifier load improves stability and lowers power dissipation.
The recommended connection diagram for the AD4021 using a single 5 volt supply appears to have a similar circuit diagram. However, the amplifier requirements are relaxed, and the Rext/Cext (R and C) values are smaller (Figure 6).
Figure 6: Typical AD4021 and ADA4807-1 application diagram powered by a single 5 volt supply with more relaxed amplifier requirements and a larger Rext value compared to driving the AD7915 discussed previously. (Image source: Analog Devices)
In Figure 6, the SAR-based AD4021 also uses a charge redistribution sampling DAC. The ADC has an on-board conversion clock and serial clock. Consequently, the conversion process does not require a synchronous clock (SCK) input. This clock configuration allows the elongation of the acquisition time, which improves the accuracy by providing more time for the input signal to settle to a final value.
The main consideration for the drive amplifier for both the AD7915 and AD4021 is noise, as the amplifier/Rext/Cext combination must settle from a full-scale step to a 16-bit level (0.0015%, 15 ppm) for the AD7915, and a 20-bit level (0.00001%, 1 ppm) for the AD4021.
To preserve the signal-to-noise (SNR) performance of the AD7915 and AD4021, the driver amplifier noise must be less than one-third of the ADC’s noise. The AD4021 noise is 60 microvolts rms (mVrms), which requires the amplifier/Rext/Cext combination to be less than 20 mVrms. The AD4021 noise is 31.5 mVrms, which requires the amplifier/Rext/Cext combination to be less than 10.5 mVrms.
The Precision ADC Driver Tool from Analog Devices helps designers quickly calculate the correct Rext and Cext values. With a selected driver and ADC, this tool models the circuit’s settling time, noise, and distortion behavior.
The SAR ADC continues to dominate ultra-high-speed data acquisition, industrial control, and instrumentation applications. However, the external input circuitry for these devices—the driving amplifier and input filter—requires special consideration to accommodate potential switching charge injection and amplifier stability issues.
The solution to precise input signal control for most SAR converters, such as the AD7916 and AD4021, lies in the op amp driver—in this case the ADA4807-1. As shown, these devices, supported by the proper output resistor and capacitor values, form a solid foundation upon which to build a high-precision, robust, high-resolution, 16-bit or 20-bit SAR converter system.