The use of serial technology for high-end system design has accounted for a large proportion. In a recent survey conducted by EETimes magazine, 92% of the respondents indicated that serial I/O systems had been designed in 2006, while only 6% had been engaged in serial design in 2005.
The prevalence of serial technology in backplane applications has greatly contributed to this increase. With increasing demands on system throughput, the older parallel backplane technology has been replaced by serializer-based (serial deserializer) ( SerDes) technology backplane subsystem.
The advent of standard serial protocols such as XAUI and Gigabit Ethernet (GbE) that help simplify design and enable interoperability has further driven the adoption of serial technology. In addition, the serial backplane specification standards such as AdvancedTCA and MicroTCA formulated by the PCI Industrial Computer Manufacturers Association (PICMG) have also played an important role in the rapid popularization of serial technology. Serial backplane technology has great advantages and is not only widely used in communication systems, computer systems, storage systems, but also in TV broadcasting systems, medical systems, and industrial/test systems.
Design “stubborn disease”
Although the use of serial technology has become increasingly common, many design challenges still lie ahead for designers. The backplane subsystem is the “heart” of the entire system and must be able to provide reliable signal transmission between boards. Therefore, ensuring high signal integrity (SI) is a top priority in backplane design.
In addition, it is also crucial to use the appropriate chip based on SerDes technology that can drive the backplane with a very low bit error rate. Utilizing chip components to improve SI is especially important in “early system upgrade” applications where designers reuse older components and design rules from older backplanes.
Developing serial backplane protocols and fabric interfaces is also a challenge for designers. Most backplane designs utilize early application-specific integrated circuits (ASICs) with proprietary protocols, and even some newer backplane designs require proprietary backplane protocols. Therefore, the chip solution must be flexible enough to support the necessary customization. While ASICs can achieve this, ASICs are often costly and risky due to uncertainty in product demand/sales, possible design flaws, changes to technical specifications, etc.
Recently, modular switching fabrics based on existing standards have gradually become a hot technology. This technology helps shorten development cycles, but the chip solutions employed must support standard protocols and allow flexibility for unique customization of the final product. Of course, there are unavoidable challenges such as cost, power consumption, and time-to-market. To address this series of challenges in serial backplane design, Xilinx has introduced the Virtex-5LXT FPGA platform and IP solutions.
Serial Backplane Solutions
The key technology of the Xilinx Virtex-5LXT FPGA for serial backplane applications is the embedded RocketIO GTP low-power serial transceiver. The largest Virtex-5LXTFPGA can contain up to 24 serial transceivers, each operating at a rate ranging from 100Mbps to 3.2Gbps. Combined with the programmable fabric, the FPGA can support almost any serial protocol, whether proprietary or standard, at rates up to 3.2Gbps.
More important for serial backplane applications are the built-in signal conditioning features, including transmit pre-emphasis and receive equalization techniques. These features enable signal transmission over long distances (often up to 40 inches or more) at rates up to several gigabits. Both equalization methods minimize the effects of inter-symbol interference (ISI) by enhancing high-frequency signal components and attenuating low-frequency signal components. The difference is that pre-emphasis is performed on the transmit signal output by the line driver, while receive equalization is performed on the receive signal coming into the IC package. Both the pre-emphasis and equalization features are programmable to different states for optimal signal compensation.
In addition to the signal conditioning features, these serial receivers have other backplane useful features, such as programmable output swing, which enables interfacing with a variety of other current-mode logic (CML)-based devices and built-in AC Coupling Capacitors – Simplifies transmission line design and reduces ISI.
Most serial backplane applications still use proprietary protocols. However, some recent new designs have begun to adopt standardized protocols such as XAUI and GbE. This is mainly because, on the one hand, these standards are becoming more and more mature, and on the other hand, switch fabric specific standard products (ASSPs) based on these protocols are also emerging. Using ASSP to implement switching applications can greatly shorten the development cycle, but designers have found that product differentiation must be achieved by providing value-added functions (mainly on-line cards).
Because these serial transceivers are designed to support most serial backplane standard protocols, FPGAs are ideal platforms for implementing custom features. Together, the serial transceiver and switch interface allow for a standards-compliant design with value-added features, all on a single chip device.
To help shorten design cycles, Xilinx offers modular IP cores for major serial I/O interface standards such as XAUI, GbE, SRIO and PCIe. To ensure interoperability, these IP cores have undergone a series of compatibility tests and independent third-party verification. To help produce “lightweight” serial protocol designs, Xilinx has also introduced the Aurora protocol — especially for simpler designs that require minimizing overhead and optimizing chip resource utilization.
Due to the widening application of Ethernet and PCIe technology, Virtex-5LXTFPGA also implements embedded tri-state Ethernet MAC and PCIe endpoint modules. These features can help save significant FPGA resources, for example, for customers who need to implement interfaces in control board applications.
At present, even some newer systems are still using parallel interface chips, so Xilinx has also introduced IP cores for common parallel interfaces such as SPI-4.2, SPI-3, and PCI to quickly design serial-to-parallel bridges, meet the needs of many applications.
In addition to serial and parallel interface IP cores, Xilinx also provides more complete IP solutions to further shorten product development cycles and time-to-market. Includes a traffic manager to optimize backplane traffic and a mesh reference design that allows “many-to-many” connectivity between boards. In addition, the ChipScope Pro serial I/O tool suite helps designers quickly set up and debug serial transceivers, as well as perform BERT testing.
Below is an example of how all of these solution elements can be integrated to create a complete serial backplane interface FPGA for star and mesh systems.
1. Star backplane topology application
The star backplane topology is very economical, especially in systems with a large number of boards, so a large number of high-end infrastructure devices use the star topology. Figure 1 shows an example of a 10GbE line card that implements an FPGA-based star-switched interface. The FPGA instantiates a XAUI LogiCORE IP core connected to a 16-channel XAUI switch fabric card using 4 serial transceivers. In addition, the FPGA has a LogiCORESPI-4.2 core to connect to the 10Gbps network processing unit.
Figure 1: Star-structured I/FFPGA in a 10GbE line card.
Between the serial and parallel interfaces is the Traffic Manager IP solution, which is responsible for performing Quality of Service (QoS) related functions on incoming and outgoing traffic. The memory controller is responsible for controlling the external memory that is primarily used as a packet buffer. The advantages of this architecture include increased integration of SerDes and logic functions, accelerated time-to-market with IP solutions, and implementation of customer-specific system specifications. It can also provide good signal integrity and low SerDes power consumption (total power consumption is only about 400mW). Customers can implement all of this on the XC5VLX50T device.
While most systems use a star topology, some smaller systems require a mesh topology. For example, the 5-slot IP DSL access multiplexer shown in Figure 2 requires full connectivity between four 24-port VDSL line cards and a 10GbE backhaul card connected to Metro Ethernet. Each board utilizes a Virtex-5LXT device and four embedded serial transceivers to implement four independent mesh physical layer channels. These 4 link layers are based on the Aurora protocol and transmit 2.4Gbps payload and other overhead such as encoding at around 3Gbps.
Figure 2: Mesh I/FFPGA in a 10GbE line card.
The trunk card (trunk card) and the line card use SPI-4.2 and SPI-3LogiCOREIP cores respectively to provide the connection function for the network processor. The mesh reference design and traffic manager solution provides distributed switching and QoS capabilities for all line cards.
The line card logic interface can be easily loaded onto the XC5VLX30T device, while the trunk card interface structure can be loaded onto the XC5VLX50T device. Similar to the star system example, the Virtex-5LXT solution can improve integration, shorten time to market, optimize system features, reduce power consumption and cost, and more.
Conclusion of this paper
Today, serial backplane technology is mainstream. As bandwidth requirements increase, more and more applications will use serial backplane technology. At the same time, the backplane subsystem will inevitably have higher and higher requirements on rates and protocols, and designers will face an endless stream of new challenges.
However, with the XilinxVirtex-5LXTFPGA and existing IP solutions for serial backplanes, system fabric designers can choose between upgrading earlier systems and designing new backplanes. The Virtex-5LXTFPGA with embedded SerDes has key features designed to improve SI and the high level of integration required to achieve highly reliable, area and cost optimized designs.