A paper analyzes the driving of inductive loads of power MOSFETs

This application note describes the process of designing a LITTLEFOOT® power MOSFET in a surface mount package. It describes driving inductive loads for power MOSFETs, common gate driver as well as disk drive applications and common gate stage driving capacitive loads.

This application note describes the process of designing a LITTLEFOOT® power MOSFET in a surface mount package. It describes driving inductive loads for power MOSFETs, common gate driver as well as disk drive applications and common gate stage driving capacitive loads.

Vishay Siliconix’s LITTLE FOOT power MOSFETs pack powerful power handling capabilities into tiny surface mount packages. The 8-pin SOIC package outlined by the standard (Figure 1) has a copper leadframe to maximize heat transfer while maintaining full compatibility with existing surface mount technologies. Complementary n-channel and p-channel Si9942DY LITTLE FOOT devices can be used to directly drive inductive loads such as motors, solenoids and relays, or as low impedance buffers to drive higher power MOSFETs or other capacitive loads.

Small foot packing size

Small foot devices offer measurable advantages in a variety of low voltage motor drive applications. In computer hard disks, key characteristics such as track density, seek time and power consumption are directly related to the efficiency of the spindle motor and head actuator drive circuits. Disk drives must get their maximum motor performance from the low-voltage power supply (traditionally, a well-regulated 12 V supply) provided by the computer system. The advent of sophisticated full-featured portable computers brought new performance expectations for battery-powered systems (and 5V operation).

The Si9942DY can also be used as a buffer stage in power conversion applications to drive high capacitance power MOSFET gates at the high frequencies used in modern designs. For example, capacitive loads in excess of 3000 pF can be efficiently switched at rates greater than 1 MHz by using the Si9942DY to buffer the output of a high-efficiency CMOS PWM controller. This switching capability greatly expands the output power range of CMOS switch-mode ICs.

Driving inductive loads

When using power MOSFETs to drive inductive loads, several parameters that might otherwise be of secondary concern become very important. One characteristic of inductive loads is flyback energy. When the Inductor drive current is interrupted, unless a diode is used to clamp the voltage and freewheel the inductive flyback current, a damaged flyback voltage can result. Each power MOSFET contains a fast-recovery intrinsic diode that acts as a reliable and efficient clamp for induced flyback energy. Of particular importance when using a MOSFET’s reverse characteristics are its inherent diode specifications – V SD (reverse source-drain voltage, i.e. diode forward voltage drop) and t rr (reverse recovery time).

The flyback current circulating through the diode clamp is equal to the motor current, which reaches its maximum level during motor acceleration or braking. Although the power loss in the clamp diode (V SD multiplied by the recirculation current) is only a small fraction of the duty cycle, if the forward voltage drop is too large, it can contribute significantly to the overall heating of the MOSFET. Each half-bridge is specified with a maximum forward voltage drop of 1.6V for both the n-channel and p-channel devices at the MOSFET’s maximum (continuous) forward drain current rating.

Clamp Induced Flyback Energy

When the driver is re-enabled in the same path, although the flyback current is still circulating in the opposing clamp diode, it must recombine before the diode recovers and blocks the voltage (Figure 2).

Clamp Induced Flyback Energy

Universal door drive

A common reason for simultaneous conduction is to connect the p-channel and n-channel gates together and drive them from a common logic signal. While this may be a perfectly acceptable gate drive method for capacitive loads or lower voltage systems, it may result in excessive crossover currents when driving 12 V inductive loads across the bridge. If the gates are driven together, the correct output state will be obtained. However, this comes at the cost of when the common gate voltage transitions between approximately 2 V (n-channel threshold voltage) and 8 V (12 V minus p-channel threshold voltage), since both devices are partially on the cost of the current spikes caused).

disk drive application

Using dual MOSFETs with p-channel and n-channel devices allows for the simplest gate drive circuit, as both gates can be grounded or a 12 V supply. The half-bridges typically used to drive each phase of a spindle motor (Figure 3) or head actuator (Figure 4) are driven directly by the outputs of standard CMOSlogic devices powered by the same 12 V supply. Although the relatively high output impedance of CMOS logic devices will not drive the capacitive gates of the half-bridge hard enough to achieve maximum switching speeds, this combination will provide slew rates fast enough to result in tolerable switching losses. Driving the power MOSFET gate with a lower impedance driver will result in a faster transition rate and further reduce switching losses. However, designers are often forced to strike a balance between switching losses and increased EMI/RFI. This is of particular concern in spinning disk drive storage.

12V, Three Phase Permanent Magnet Brushless Motor Driver

12V H-Bridge Actuator Driver

Submersible capacitive load

High-efficiency CMOS devices are a natural complement to the low-loss power-handling capabilities of power MOSFETs. However, the CMOS output has relatively high impedance, while the power MOSFET gate has high capacitive. If high frequencies are required, some type of gate drive buffer must be used. The Si9942DY will work perfectly in this application as a very low impedance complementary output stage for a CMOS device. The gate capacitance is easily driven by standard CMOS outputs, while a single-stage complementary pair adds minimal delay.

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